With the increase in the amount of data that computing systems generate, collect, and process, there has been an increasing demand for data throughput between computer processors that execute the operations of the computing devices and the memory which stores the data for execution. The interface between the processor and the memory devices can become a bottleneck in the overall performance of the computing device. One approach to reduce the bottleneck between the processor and the memory devices is to replace part or all of the data with a predefined data pattern inside the memory when writing data into the memory array. For example, for a frequently occurring data pattern such as all-zeros or all-ones, instead of sending the actual data over the data channel from the controller to the memory, a new signal can be created to generate and replace this frequently occurring data pattern inside the memory. Replacement of the data reduces the transfer of data on the data bus, which can improve I/O (input/output) power and data bus utilization efficiency. However, additional signal lines increases the required hardware and pinout, which is not desired, and inefficient circuits and data write operations at the memory device can reduce the efficiency gains that data pattern replacement or substitution could provide.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.